1. Field
The present embodiment relates to current-controlled oscillators, and particularly to a current-controlled oscillator in which an oscillation frequency is changed in accordance with control current.
2. Description of the Related Art
Oscillators controlled by current or voltage are widely used in basic parts of data communication systems such as a clock recovery circuit and a phased lock loop (PLL) in a bit synchronization block. These oscillators include current-controlled oscillators using two grounded capacitors and voltage-controlled oscillators (for example, refer to: M. Flynn and S. Lindholm, “A 1.2-μm CMOS Current-Controlled Oscillator,” In IEEE Journal of Solid State Circuits, Vol. 27, No. 7, pp. 982-987, July 1992; M. Banu, “MOS oscillators with multi-decade tuning range and gigahertz maximum speed,” IEEE J. Solid-State Circuits, vol. 23, pp. 1386-1393, December 1988; and Japanese Unexamined Patent Application Publication No. 08-265108).
FIG. 9 is a schematic diagram of a conventional current-controlled oscillator using two grounded capacitors. As shown in the figure, the current-controlled oscillator includes PMOS transistors M101, M103, and M105 to M107, NMOS transistors M102 and M104, capacitors C101 and C102, a current source I101, comparators 101 and 102, and an RS flip-flop 103.
The transistors M101, M102, and M106 and the capacitor C101 form one delay circuit, and the transistors M103, M104, and M107 and the capacitor C102 form another delay circuit. Oscillation signals are generated through alternate charging and discharging of the capacitors C101 and C102 of the individual delay circuits.
The transistors M105, M106, and M107 form current mirror circuits. The current mirror circuits return current from the current source I101 to the transistors M106 and M107.
In the delay circuit that includes the transistors M101 and M102, when a low signal is input to their gates, the transistor M101 is turned on, and the transistor M102 is turned off. This causes the capacitor C101 to store current (electric charge) from the transistor M106. When a high signal is input to the gates of the transistors M101 and M102, the transistor M101 is turned off, and the transistor M102 is turned on. This connects the capacitor C101 to a node of a voltage Vss (the ground voltage of a power supply having a voltage Vdd), and the stored electric charge is discharged. Like the transistors M101 and M102 and the capacitor C101, the transistors M103 and M104 and the capacitor C102, which form the other delay circuit, charge and discharge current flowing from the transistor M107.
The voltages across the capacitors C101 and C102 are input to the comparators 101 and 102 respectively. The comparators 101 and 102 receive a reference voltage Vref, compare the voltages of the capacitors C101 and C102 with the reference voltage Vref, and output the comparison results to the flip-flop 103. For instance, the comparator 101 or 102 outputs a high signal when the voltage across the capacitor C101 or C102 is higher than the reference voltage Vref.
In the flip-flop 103, the signal from the comparator 101 is input to an “S” terminal, and the signal from the comparator 102 is input to an “R” terminal. When the signal input to the “S” terminal goes high, the flip-flop 103 outputs a high signal from a “Q” terminal. In other words, when the capacitor C101 stores electric charge to a voltage level exceeding the reference voltage Vref, the flip-flop 103 outputs a high signal from the “Q” terminal. The high signal output from the “Q” terminal is output to the gates of the transistors M101 and M102. This turns on the transistor M102, and the capacitor C101 discharges the electric charge.
The high signal input to the “S” terminal causes the flip-flop 103 to output a low signal from an “XQ” terminal. This turns on the transistor M103, and the capacitor C102 stores electric charge. When the capacitor C102 is charged to a voltage level exceeding the reference voltage Vref, the comparator 102 outputs a high signal. The high signal is input to the “R” terminal and causes the flip-flop 103 to output a low signal from the “Q” terminal and a high signal from the “XQ” terminal. This causes the capacitor C101 to store electric charge and the capacitor C102 to be discharged.
The alternate charging and discharging of the capacitors C101 and C102 provide oscillation signals from nodes N101 and N102 shown in the figure. By controlling the amount of current of the current source I101, the charging speed of the capacitors C101 and C102 can be changed, and the frequency of the oscillation signals can be changed.
FIG. 10 is a view illustrating the charging and discharging of a capacitor. Lines W101 and W102 shown in the figure represent changes in voltage across the capacitor C101 (node N101). Lines W103 and W104 represent changes in voltage across the capacitor C102 (node N102).
As the line W101 indicates, current flowing from the transistor M106 increases the voltage across the capacitor C101. When the voltage across the capacitor C101 reaches the reference voltage Vref input to the comparator 101, electric charge is discharged, as indicated by the line W102, and the capacitor C102 stores electric charge, as indicated by the line W103. When the charging brings the voltage level across the capacitor 102 to the reference voltage Vref, the capacitor C102 discharges electric charge, as indicated by the line W104. The charging and discharging repeated by the capacitors C101 and C102 produce the oscillation signals.
A period T of the current-controlled oscillator shown in the figure is given by the following expression (1).T=2(C*Vref/Ic+Td)  (1)
where C is the capacitance of the capacitors C101 and C102, Ic is current flowing through the capacitors C101 and C102, and Td is a delay time caused by the comparators 101 and 102 (period taken to compare the voltages). Therefore, the frequency f of the oscillation signal can be given by the following expression (2).f=Ic/{2*(C*Vref+Td*Ic)}  (2)
FIG. 11 is a view showing the relationship between the current stored in a capacitor and the frequency of the oscillation signal. A line W111 in the figure represents an ideal relationship between the current of the current source I101 and the frequency. A line W112 represents an actual relationship between the current of the current source I101 and the frequency. It is desired that the frequency of the oscillation signal increase in proportion to the increase in current of the current source I101, as indicated by the line W111.
The expression (2) has Ic in the numerator, which means that an increase in current of the current source I101 increases the frequency. However, the denominator also includes Ic, which makes the relationship non-linear, as indicated by the line W112. The delay time Td caused by the comparators 101 and 102 makes the current-frequency relationship non-linear. Consequently, an increase in current of the current source I101 does not increase high frequencies, narrowing the frequency range. The delay caused by the comparators 101 and 102 includes the intrinsic delay of the comparators 101 and 102 and a delay caused by the parasitic capacitance of the transistors M101 to M104 connected to the input stage and the capacitance of the capacitors C101 and C102.